The present disclosure relates to integrated circuit device manufacturing processes, especially self-aligned double patterning.
In conventional photolithography, a photoresist is exposed to light through a mask. The photoresist is modified by the exposure in such a way that either the exposed or unexposed portions of the resist can be removed during subsequent development. Any photolithographic process has limitations, whereby there is a critical dimension below which features are too fine to be resolved. That resolution limit is a barrier in reducing the scale of integrated circuit devices.
Self-aligned double patterning is a technique for forming features having a finer pitch than would be possible by the direct application of a photolithographic process. Self-aligned double patterning involves forming a mandrel having line-shaped features. A spacer formation process is then used to form spacers on the sides of the mandrel features. The mandrel can then be stripped leaving the spacers defining two sets of lines. A first set of lines (L1 lines) corresponds to line-shaped features of the mandrel. A second set of lines (L2 lines) corresponds to the spaces between adjacent line-shaped features of the mandrel.